hello to everyone BY voay2429 Introduction to Layout design Note: some figures are taken from Ref. B. Razavi, Design of Analog CMOS integrated circuits, Mc Graw-Hill, 2001 , and MOS’S web site: http://www. mosis. org/ E.
Martinez-Guerrero nailer de Diseno Fistco / MDE DESI ITES0/0tono 2006 Introduction to layout design Layout consist in: Draw geometrical objects of different layers, Make arrays of geometrical objects, Patterns Make blocks of arrays for the core, interface, for the and padframe. fabrication the Interconnect blocks and interfaces to the “masks” padframe, All the layout must satisfy “design rules”Why design rules? 2 Layers for designs masks used by L-Edit Default SCNA CMOS Layers Physical layer Name Color N-well N-WELL TAN dashed SiN3 ACTIVE Polysilicon 1 POLYI RED filled Polysilicon 2 POLY2 BLACK filled Contact to poly POLY CONTACT P+ Ion implant PSELECT RED dashed N+ Ion implant NSELECT contact to N+/P+ ACTIVE CONTACT Metal 1 METAL 1 BLUE filled Metal 2 GREY filled Via oxide cuts VIA WHITE filled Pad contacts OVERGLASS Purple crosshatch 3 Considerations in layout of CMOS s Bastc layout of a MOSFET 4 Changes in W due to tolerances in the fabrication process oxide encroachment FOXDrawn Width bird’s beak gate oxide w DW/2 p-substrate ideal real 5 Changes in L due to tolerances in the fabrication process: Length Drawn “Lateral diffusion” FOX p+FOX n-well FOX PFOX DU2 6 ??? Minimize unwanted diffusion ??? Use minimum poly width (2X) 7 Consideration in layout of CMOS Compensating encroachment oxide and lateral diffusion: Due to oxide encroachment, the effective channel width of MOSFETs is smaller than the drawn width.The BSIM SPICE model gives the DW to consider oxide encroachment Weff= WM – DW where WM is the drawn width, DW is twice the oxide encroachment. Similarly, due to ateral diffusion, the effective channel length is smaller than the drawn length.
The BSIM SPICE model gives the LD and DL parameters to consider lateral diffusion and the changes due to lithography. Leff= LM – 2LD – DL Where LM is the drawn length, LD is the interdiffusion and DL is the reduction because of lithography. Changes in W due to tolerances in the fabrication process: “shadow effect” D & S Asymmetry: avoid channeling shadowed region asymmetry 9 Compensating the shadow effect The asymmetry caused by the shadowing can be ameliorated: assume that transistors are placed parallel as indicated in the Fig.
; if the shadowed terminal is D (or S), then the two devices sustain no asymmetry resulting from shadowing. if transistor are placed as in the Fig. b; one can add dummy transistors to the two sides of transistors, so that Tl and T2 see approximately the same environment. Fig. b Fig. Dummy 10 Antenna Effect: During the etching of metall layer, the metal area acts as an “antenna”, collecting ions and then rising in potential, therefore the gate voltage can increase so much that the gate oxide breaks down during fabrication. layout susceptible to antenna effect (MOSFET tied to a metal 1 layer having a large area) Antenna Effect Compensation: If large area are inevitable (Fig. a), then a discontinuity can be discontinuity in metal 1 layer to avoid 11 Parasitic Bipolar transistors in CMOS technology NPN NPNP PNP CMOS Latch-up this device will turn on the other parasitic as well.
Each Q supplies the other’s Base current. Once both Qs begin to conduct they will continue to do so even if the transient disturbance that initiated conduction is removed. The circuit has latched up and it will remain in this state until power is removed. The integrated circuit can actually conduct so much current that it overheats and selfdestructs.
Even if this does not occur, latch up causes circuit malfunction and excessive supply current consumption. 2 Minimizing Latch-Up Sensitive analog circuit shielded by the guard ring Some approaches to reduce latch up Eliminate the forward biased junctions that cause the problem; simple but difficult to achieve Increase the spacing between components. Separate potential injectors from sensitive circuitry, i. e. place power transistors far away of sensitive input circuitry. Increase doping concentrations. CMOS and BiCMOS processes often employ P+ substrates to reduce the gain of parasitic Qs.
Bondpad Guard ring Provide alternate collectors to arriers. Use a heavily doped isolation or add suitable guard rings. 3 B contact PMoat guard ring (hole collecting) NMoat guard ring (electron collecting) 14 Design Rules for Layout 15 Design rules The Design Rules are related to manufacturing constraints and tolerances. There are two systems of rules: Specific values (usually in microns, although there are other possibilities; mils, millimeters, centimeters or inches).
Scalable (multiples of some metric typically h of the technology) for maximum flexibility. There are five types of Design Rules Minimum width Exact Width Minimum space Surrounding Overlap and Extend 16