Developing demands and the market show two main trendshelping to shape the ongoing development of system integration technologies.First of all is an ongoing increase in the number of functions directlyincluded in a system — such as electrical, optical, mechanical, biological andchemical processes — combined with the demand for higher reliability and longersystem lifetime. Second is the increasingly seamless merging of products andelectronics, which necessitates adapting electronics to predefined materials,forms and application environments. Only by these means systems sensors — whichare often installed in extremely harsh environments — and signal processing canbe implemented near to the point where signals are occurring.

Largearea mold embedding technologies and embedding of active components intoprinted circuit boards (Chip-in-Polymer) are two major packaging trends in thisarea. Both technologies are under the frame of Panel Level Packaging researchat Fraunhofer IZM. This paper describes the potential of heterogeneous integration technologies researched at Fraunhofer IZMwith a strong focus on embedding in printed circuit boards and embedding inmolded reconfigured wafers withan outlook of advanced large area encapsulation processes for multi chipembedding in combination with large area and low cost redistribution technologyderived from printed circuit board manufacturing.  IntroductionMostelectronic systems available today are realized through an organic printedwiring board, on which the individual components are placed. The wiring boardis exclusively used with regard to electrical and mechanical function. Howeverthere are numerous attempts and necessity in the development of modernelectronic products, which have to lead to the integration of further systemfunctions into the board.Futureboard and substrate technologies have to ensure a cost efficiently integrationof highly complex systems, with a high degree of miniaturization and sufficientflexibility in adaptation to different applications.

Their functionality willbe considerably enlarged by integration of non-electronic functions such asMEMS, antennas or optical components. New production methods will ensure a highthroughput at very low cost. To ensurehigh data transmission and processing rates new cost effective coolingtechnologies and 3D-Packaging concepts will ensure a stable operation mode. Thefollowing priorities are seen for multi functional board and substratetechnologies:§  Embedded devices technologies like active  components (ICs), MEMS, passives, antennasand others§   Ultra fine linesand space technology with smaller vias for low cost substrates and interposers §  Impedance controlled wiring §  Flexible substrates (reel to reel manufacturing) §  Integrated optical interconnects To reachthese priorities new materials for embedding and encapsulation have to bedeveloped with the following properties:§  High K and low K dielectrics§  High Tg polymers with low curing temperature§  CTE matching between dies and substrate§  Optical transparency at different wavelengths used inphotonicsOn the following pages an overview will begiven on the recent technological developments towards heterogeneously integratedSiPs, focusing on embedding technologies.  Embeddinginto PCBWhile the initial concept of using active circuitryembedded into the substrate has seen its first conceptions as early as 1970, ittook nearly 30 years to be picked up by academia and industrie´s R&D. Thetipping point was actually the availability of additive HDI substratetechnology and thin active chips with compatible pad metallization at a decentquality level.TheEU-funded project “HERMES” ihas initiated, with wide participation of European industries and researchinstitutes, advancing the embedding technology borders at R&D level andmore importantly of bringing embedding technology in real manufacturing PCBproduction ii.

However,it should be underlined, that the shift to embedding technologies marks alsonecessary adaptations to the supply chain which will potentially burden thevalue system. For instance, the necessity of RDL layer for chip pitchenlargement that makes chip components compatible with existing embeddingcapabilities or copper pad deposition should be definitely accounted for beforethe shift in embedded packages. Initial applications for embedded packages willbe low cost, low pin counts applications such as analog and power devices(DC/DC converters, Power MOSFETS etc.)iii.  In a number of European cooperation projects withpartners from industry and research, embedding of power chips, like IGBTS andpower MOSFET, is of high interest iv.The dominating technology for power chip embedding is a face-up technology.Chips are bonded with their backside (drain contact) to a Cu substrate usinghighly conductive adhesive or solder.

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Using the face up assembly, a directcontact to the backside of the die is possible, allowing a lot of benefits fordriving high currents and applying an efficient thermal management for thepower devices. Then the chips are embedded by vacuum lamination of prepreg orRCC (resin coated copper) layers. Via holes to the top contacts (gate andsource) are formed by laser drilling. The vias are metalized using conventionalCu plating. Finally conductor structures are etched in the top Cu layer,finalizing the circuit.    Power Components Embedded in PCBThe combination of two or more embeddeddies e.g. MOSFET or diodes, but also controller chips, results in embeddedPower System-in-Packages (Figure1).

Here the embedding technology offers a variable technology platform for therealization of a large variety of packages on the same process line. One bigadvantage of such packages is their short interconnects, resulting in lowinductances which allow faster switching speed. Figure 1: Embedded Power SiPIn thecontext of introducing Wide-Band-Gap-Power semiconductors (WBG) like siliconcarbide (SiC) and gallium nitride (GaN), the discussion about developing powersystems in package raised to a new level.

Including part of the driver and theDC-link into the package, plus an output inductor and/or a transformer, helpsto make full use of the possibilities offered by very fast switching devicesand thus high switching frequencies. For being able to switch fast with up to500 kHz and yet keep losses and EMI issues small, packages with very lowand well known parasitic characteristics are needed (Figure2). Besides theelectrical package design, thermal management is another big challenge.    Figure 2: Example for an EMIoptimized SiC package with part of the driver and theDC-link included  Embeddinginto Molding CompoundsThere are two main approaches for embeddeddie technologies:           First, there is the ChiP technology, the embedding of active dies into PCB asdescribed above.     Second, there is wafer level integration (FOWLP), where dies are embedded intopolymer encapsulants and 3D vertical integration, where dies are embedded intothe substrate.

For wafer level integration a lot of activities are runningworldwide. Main drivers are here the Embedded Wafer Level Ball Grid Array(eWLB) by Infineon vand the Redistributed Chip Package (RCP) by Freescale vi. FOWLP has started in volume for mobile andwireless applications (mainly wireless baseband) and is now moving toautomotive and medical applications. Infineon started with a 77 GHz Radar ICChip Set (RASICTM).

RTN7735PL and RRN7745P are the first 77 GHz solutions basedon an eWLB package instead of a bare-die. They form a scalable platformcomprising a three-channel transmitter and a four-channel receiver to buildlong- and mid-range system.In general the fan-out technology is an extensionof the wafer level packaging which is optimal chip-scale package (CSP) forlowest cost, smallest size and best electrical performance. This package wasthe only possibility to solve the dilemma for moving flip-chip assembly toprinted wiring boards (PWBs).The main limitation of WLP using RDL issimple the fact that only the die surface can be used for the BGA pattern. Afiner bump pitch requires a higher routing density on the substrate that willbe used for the next level of packaging.

In addition, the bumps have to besmaller to feed the smaller BGA pitch; therefore, the reliability of assembledWLPs is reduced. Fan-out WLP has therefore been developed to stay on a relaxedBGA pitch through the creation of additional space by embedding the chips orother components into the planar molding compound. For that technology singulateddies are assembled on an intermediate carrier and encapsulated by compressionmolding, forming a polymer wafer with embedded silicon dies. This”reconfigurated” wafer is then released from the carrier. Using thin filmtechnology, an electrical redistribution layer is routed on the wafer. Finally,the wafer is singulated by sawing into single packages. One trend in eWLBtechnology is at the moment a double sided eWLB packaging with integration ofvias through the encapsulant by integration of preformed PCB based viasallowing the stacking of eWLB packages vii. The combination of both concepts embeddinginto polymer by molding and redistribution by PCB technologies has thepotential for highly integrated low cost packages and was successfullydemonstrated for a 2-chip LGA package viii.

The directintegration of Through Mold Vias (TMVs) can be easily integrated in suchpackages as vias are a standard feature in the PCB manufacturing process andcan be adapted for the proposed concepts of embedding into polymer by moldingand redistribution by PCB technologies. A principle draft of aPackage-on-Package assembly (PoP) based on a wafer level embedded package withPCB based redistribution technology is shown in Figure 3.Within this section the development and evaluation of such a packagingtechnology with TMVs is described.

Main advantages of FOWLP are thesubstrate-less package, lower thermal resistance and higher performance due toshorter interconnects together with direct IC connection by thin filmmetallization instead of wire bonds or bumps. Especially the inductance of theFO-WLP is much lower compared to FC-BGA packages. In addition it can be usedfor multi-chip packages for SiP. In addition Multi-Project Fanout WaferLevel Packaging has been demonstrated as an option to address heterogeneousintegration for the prototyping market. Focus is on high frequency applicationsup to 120 GHz ix.   Sensor Components Embedded inMouldFigure 3 showsan acceleration sensor package with pads on the package top side for stackingof the pressure sensor package and through mold vias (TMV) for 3D routing tothe package bottom to connect ASIC and acceleration sensor as well as thesubstrate. Figure 3: Photograph of an accelerationsensor with ASIC package, package top (left) and bottom (right)ASIC and sensor show a minimum contact pitchof 110 µm and pad size of 80×80 µm².

Die positions have been measuredafter molding and automatically used to adapt the µvia drill position to thedie pads and the wiring of the conductor lines to compensate the die shiftduring assembly and molding. Therewith, a good alignment between micro vias anddie pads could be achieved without shorts or off target positions. Figure 4depicts an X-Ray image of a manufactured acceleration and ASIC package showingthe interconnection of the top and bottom package metallization by the throughmold vias. Figure 4: X-Ray image of an acceleration sensor and ASIC package with throughmold vias (TMV) marked by red arrows?Pressure and acceleration sensor packageswere stacked and assembled on board by soldering. The final Package as shown inFigure 5allows now the functional testing of the entire sensor stack and therewith theproof of technology. Figure 5: Photograph of a demonstratorstack with acceleration and pressure sensor package PanelLevel PackagingPanel level packaging as a merge between theembedded die technology based on PWB infrastructure and the FOWLP on waferlevel.

The first being low cost by nature due to PWB technology but the supplychain is still complex because the PWB industry is not used to work with baredies. Also the routing density is not fitting the WLP demands. Tight padpitches require a redistribution of the dies before embedding ending up withhigher cost for the total package. Therefore the first products have been powermodules due to the possibilities of plating thick copper and the low number ofI/Os of the IGBTs and MOSFETs. An additional advantage of the embedding dieconcept is the existing TPV (through package via) possibility which enables 3Dpackaging. In contrast to embedding die the FOWLP approach can use existing WLPequipment mostly installed at OSATs and some of the IDMs. Cost is a major driver of technologicaldevelopments in microelectronics packaging, so the increase in size found withwafer diameters having evolved from 2″ in the 70s to 300 mm today is mimickedby embedding technology. This approach can use existing WLP equipment mostlyinstalled at OSATs and some of the IDMs.

Cost reduction has been achieved by furthermoving to 330 mm-Technology and the move to panel level processing will pushthe technology further to lower cost.  Currently,wafer form factor is mandatory for the manufacturing of mold embeddedcomponents, as cost effective thin film RDL technology is only available forcircular shapes. But with the PCB-derived redistribution layer application as afeasible fine pitch alternative, a cost effective upscaling of wafer level moldembedding to panel level molding will be a promising path.Still, the cost benefits are tightly tied tothe package size and level of integration. Cost benefits are more likely to beachieved, in the near future, for smaller and low end packages requiring 10µmand above lines/spaces (L/S). For high-density packages, especially at 2/2µm L/Sand below, technology development continues to be the main driver.

There arestill technical challenges that will have to be addressed before looking intocost benefits and potentially panel processing.Fraunhofer IZM in Berlin has started in 2017 aPanel Level Packaging consortium (PLC) with the goal to acquire basic processtechnology steps for the move to large format. All partners are the world-widetop champions in electronic packaging adding synergy to the over 50 M USD panellevel packaging line at Fraunhofer IZM in Berlin. This PLC will be aninternational, joint, pre-competitive i        For information on HERMES refer to: http://www.hermes-ect.net/ii       A. Ostmann, D. Manessis,H.

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